!Mod

The !Mod tag defines a module with a name, ports, child modules, interconnections, and other attributes. It can either represent a leaf module with implementation or a wiring level module with multiple, interconnected child nodes.

BLADE will modify its behaviour when elaborating a module based on values specified in the options array:

Option	Effect
NO_AUTO_CLK_RST	Don't create implicit clock and reset signals for this block
NO_CLK_RST	This block doesn't have any clock or reset signals, so don't try to auto-connect them when elaborating
IMP	This block is a leaf node containing implementation

Any leaf node can have a register map attached to it, this is done implicitly by #include’ing a register description into the same file as the !Mod definition - for example:

my_registers.yaml

- !Config
  order:
  - !Register [config]

- !Group
  name: config
  regs:
  - !Reg
    name     : enable
    busaccess: RW
    fields   :
    - !Field
      name : switch
      width: 1
      lsb  : 0
      reset: 0
  ...

my_mod.yaml

#include "my_registers.yaml"

- !Mod
  name   : my_mod
  sd     : My module with register map from my_registers.yaml
  options: [IMP]
  ...

Usage

- !Mod
  name       : my_module
  sd         : Short description of my module
  ld         : >
    Longer description of my module that can span multiple lines.
  options    : []
  # Declare boundary ports for this module
  ports      :
  - !HisRef [cfg,      axi4,        "Configuration port",    1, Slave,  "AXI4-Lite configuration port",                      []]
  - !HisRef [bypass,   enable,      "Input bypass signal",   1, Slave,  "Disables the block - data passes straight through", []]
  - !HisRef [data_in,  axi4_stream, "Streaming data input",  1, Slave,  "Inbound data to the block",                         []]
  - !HisRef [data_out, axi4_stream, "Streaming data output", 1, Master, "Outbound data from the block",                      []]
  # Declare child modules
  modules    :
  - !ModInst [convert,   axi4_to_axi4l, "AXI4 to AXI4-Lite", 1, "Converts from AXI4 to AXI4-Lite",  []]
  - !ModInst [registers, my_reg_blk,    "Register block",    1, "Controls for the transform block", []]
  # Declare explicit connections (for where autoconnections won't work)
  connections:
  # - Connect boundary AXI4 configuration port to the AXI4 to AXI4-Lite converter
  - !Connect
    points:
    - !Point [cfg]
    - !Point [inport, convert]
  # - Connect output of the converter to the input of the register block
  - !Connect
    points:
    - !Point [outport, convert  ]
    - !Point [cfg,     registers]
  # Tie-off unused boundary ports (where they don't connect to a child)
  defaults:
  - !Point [bypass]

class blade.schema.ph_mod.Mod(name, ports, options=None, sd='', modules=[], connections=[], conections=[], ld='', defaults=[], importhisrefs=None, requirements=None, clk_root=None, rst_root=None, addressmap=None, extends=None)

!Mod tag schema class listing ports, modules, and interconnections

__init__(name, ports, options=None, sd='', modules=[], connections=[], conections=[], ld='', defaults=[], importhisrefs=None, requirements=None, clk_root=None, rst_root=None, addressmap=None, extends=None)

Initialisation for !Mod YAML Tag

Parameters

• name – Name of the !Mod, how it will be referred to when instantiated

• ports – List of !HisRef ports on the boundary of this block

• options – List of options either in the form ‘KEY=VAL’ or just ‘KEY’ if a value is not required

• sd – Short description of the block - maximum 150 characters

• modules – List of !ModInst tags which instantiate child modules

• connections – List of !Connect tags detailing connections between ports of the block and ports of child blocks

• conections – Deprecated alias of ‘connection’

• ld – Long description of the block - no maximum length

• defaults – List of !Point tags that tie-off unused input and output ports

• importhisrefs – Deprecated attribute

• requirements – Deprecated attribute

• clk_root – !Point tag specifying which (if any) output port on the block acts as a clock generator.

• rst_root – !Point tag specifying which (if any) output port on the block acts as a reset generator.

• addressmap – A list of !Initiator and !Target tags detailing the address map between input and output ports.

• extends – Allow block to inherit and extend the definition (ports, connections, etc.) of another defined !Mod.

set_file_marks(start, end)

Set start and end marks of the declaration and propagate to children

Parameters

• start – The starting mark

• end – The ending mark

set_source_file(file)

Set the source file of this object and propagate it to children.

Parameters

file – The source file path or object

validate()

Check that this tag agrees with our YAML schema